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NVIDIA·Software Engineer·Technical Phone Screen·Senior

Senior
May 2026

Summary

NVIDIA software engineer interview that went deep on GPU architecture, specifically how thread limits and occupancy work on modern hardware. More math-heavy than I expected for what I thought would be a conceptual discussion.

Questions Asked (4)

Q1

What is the maximum number of threads per block on an NVIDIA GPU, and why does that limit exist?

System DesignTechnical Trade-offs
Author's notes

This part I actually knew cold.

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AI HintsAI Generated

Suggested Approach

Start by stating the current limit (1024 threads per block for modern GPUs) and briefly mention its historical evolution. Then explain the hardware and software reasons for the limit, focusing on resource constraints and architectural design trade-offs. Conclude by discussing the implications for performance and how developers can work within this constraint.

Pro tip: Demonstrate awareness that the limit is not just a hardware restriction but also a programming model choice that balances flexibility and efficiency. Mention that exceeding the limit requires restructuring algorithms, and show you understand the trade-offs between occupancy and resource usage.

1. State the current limit and historical context

Clearly state that the maximum number of threads per block is 1024 for NVIDIA GPUs with compute capability 2.0 and higher. Mention that older architectures had lower limits (e.g., 512 for compute capability 1.x).

2. Explain hardware constraints

Discuss how the limit arises from the need to allocate resources per block, such as registers, shared memory, and warp slots. The SM (Streaming Multiprocessor) has a finite number of resources, and each block must fit within these limits.

3. Discuss architectural design trade-offs

Explain that the limit balances parallelism and resource utilization. Too many threads per block can lead to reduced occupancy due to resource exhaustion, while too few can underutilize the SM. The 1024 limit is a sweet spot for most workloads.

4. Mention software and programming model considerations

Highlight that the CUDA programming model enforces this limit to simplify scheduling and synchronization. It ensures that all threads in a block can be resident simultaneously, enabling efficient barrier synchronization and shared memory access.

5. Conclude with implications and best practices

Summarize that developers should design blocks with a multiple of 32 threads (warp size) and typically use 128-512 threads per block for optimal performance. Exceeding the limit requires splitting work into multiple blocks.

Key Points to Mention

  • Maximum threads per block is 1024 for compute capability >= 2.0.
  • Limit is due to per-SM resource constraints: registers, shared memory, warp slots.
  • Trade-off between parallelism and occupancy: more threads per block can reduce occupancy if resources are exhausted.
  • All threads in a block must be co-resident for barrier synchronization and shared memory coherence.
  • Warp size is 32 threads; block size should be a multiple of 32 for efficiency.
  • Historical context: older GPUs had lower limits (e.g., 512 threads per block).

AI-generated suggestions, not part of the candidate's original notes. May be inaccurate — verify before relying on them.

Q2

What are the different factors that limit the number of resident threads on a Streaming Multiprocessor simultaneously?

System DesignTechnical Trade-offs
Author's notes

There are four real constraints here: warp count limits, block count limits, register file pressure, and shared memory capacity.

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AI HintsAI Generated

Suggested Approach

Start by clarifying that the number of resident threads on an SM is limited by a combination of hardware resource constraints and architectural limits. Then systematically explain each factor, emphasizing how they interact to determine occupancy, and conclude with how this impacts performance and design trade-offs.

Pro tip: Mention that occupancy is not the only goal; sometimes lower occupancy with better instruction-level parallelism yields higher performance. This shows you understand the nuance beyond just maximizing thread count.

1. Define the concept

Explain that resident threads are those actively residing on an SM, and the maximum is determined by multiple hardware limits. Clarify that this is about occupancy, not just theoretical maximum.

2. List hardware resource limits

Enumerate the key hardware constraints: maximum threads per SM, maximum blocks per SM, registers per SM, shared memory per SM, and warp slots. Explain how each can become the bottleneck.

3. Explain per-thread resource usage

Discuss how per-thread register usage and per-block shared memory usage affect the number of blocks that can be resident, thus limiting total threads. Mention that these are often the practical limiting factors.

4. Discuss architectural limits

Cover fixed limits like maximum warps per SM, maximum blocks per SM, and maximum threads per block. Note that these are hard limits imposed by the GPU architecture.

5. Summarize interaction and trade-offs

Conclude that the actual number is the minimum of all these constraints, and that optimizing for occupancy involves balancing resource usage. Mention that higher occupancy doesn't always mean better performance.

Key Points to Mention

  • Maximum threads per SM (e.g., 2048 on many architectures)
  • Maximum blocks per SM (e.g., 32 on many architectures)
  • Register file size per SM and per-thread register usage
  • Shared memory per SM and per-block shared memory usage
  • Warp slots and maximum warps per SM
  • Occupancy calculation and its impact on latency hiding

AI-generated suggestions, not part of the candidate's original notes. May be inaccurate — verify before relying on them.

Q3

Given a kernel's per-thread register usage and per-block shared memory usage, how would you compute GPU occupancy?

System DesignTechnical Trade-offs
Author's notes

This is where it got uncomfortable.

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AI HintsAI Generated

Suggested Approach

Start by explaining that occupancy is the ratio of active warps per SM to the maximum supported warps, limited by registers, shared memory, and other factors. Then walk through the step-by-step calculation: determine per-SM limits from registers and shared memory, take the minimum, and compute occupancy. Finally, discuss trade-offs and how to improve occupancy if needed.

Pro tip: Mention that occupancy is not the only goal—sometimes lower occupancy with higher ILP yields better performance. Also, note that modern GPUs have register file sizes and shared memory capacities that vary by architecture, so always check the specific compute capability.

1. Define occupancy and identify limiting factors

Explain that occupancy is the ratio of active warps to the maximum warps per SM. The main limiting factors are registers per thread, shared memory per block, block size, and hardware limits.

2. Calculate register-limited blocks per SM

Compute the number of registers per block (registers per thread × threads per block). Then divide the total registers per SM by this number, rounding down, to get the maximum blocks per SM due to registers.

3. Calculate shared memory-limited blocks per SM

Divide the total shared memory per SM by the shared memory per block, rounding down, to get the maximum blocks per SM due to shared memory. Also consider any static shared memory overhead.

4. Determine actual blocks per SM and occupancy

Take the minimum of the register-limited and shared memory-limited blocks per SM, and also consider the hardware limit on blocks per SM. Then compute occupancy as (blocks per SM × threads per block) / max threads per SM.

5. Discuss trade-offs and optimization

Explain that higher occupancy is not always better; sometimes lower occupancy with more ILP is faster. Mention techniques to improve occupancy: reducing register usage (e.g., via compiler flags), reducing shared memory, or adjusting block size.

Key Points to Mention

  • Occupancy = active warps / max warps per SM
  • Registers per thread and shared memory per block are key constraints
  • Hardware limits: max registers per SM, max shared memory per SM, max blocks per SM, max threads per SM
  • Rounding down when calculating blocks per SM
  • Occupancy is not the sole performance metric; ILP and memory access patterns matter
  • Use CUDA Occupancy Calculator or API (cudaOccupancyMaxActiveBlocksPerMultiprocessor) for precise calculation

AI-generated suggestions, not part of the candidate's original notes. May be inaccurate — verify before relying on them.

Q4

How does occupancy influence how you choose your kernel launch configuration, and what are the performance tradeoffs involved?

Technical Trade-offsSystem Design
Author's notes

Counterintuitively, higher occupancy isn't always better.

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AI HintsAI Generated

Suggested Approach

Start by defining occupancy and its relationship to latency hiding, then explain how you use it to guide launch configuration decisions. Discuss the tradeoffs between occupancy and other performance factors, and emphasize a measurement-driven approach.

Pro tip: Mention that maximizing occupancy isn't always optimal; sometimes lower occupancy with better instruction-level parallelism or cache usage yields higher performance. Always validate with profiling tools like Nsight Compute.

1. Define occupancy and its purpose

Explain that occupancy is the ratio of active warps to maximum warps per SM, and its primary role is to hide memory and instruction latency.

2. Explain how occupancy guides launch configuration

Describe how you use occupancy calculators or APIs to choose block size and shared memory usage, aiming for enough active warps to saturate execution units.

3. Discuss performance tradeoffs

Cover tradeoffs such as increased register pressure reducing occupancy, shared memory limiting blocks per SM, and how higher occupancy can sometimes hurt due to cache thrashing or reduced ILP.

4. Emphasize measurement and iteration

Stress that theoretical occupancy is a starting point; actual performance requires profiling and tuning with real workloads.

Key Points to Mention

  • Occupancy as a latency-hiding mechanism
  • Factors affecting occupancy: registers, shared memory, block size
  • Tradeoff: occupancy vs. instruction-level parallelism
  • Tradeoff: occupancy vs. cache locality
  • Using CUDA occupancy APIs and profilers (e.g., cudaOccupancyMaxPotentialBlockSize, Nsight Compute)
  • Case where lower occupancy yields better performance

AI-generated suggestions, not part of the candidate's original notes. May be inaccurate — verify before relying on them.