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Waymo·Machine Learning Engineer·Technical Phone Screen·Senior

Senior
Apr 2026

Summary

Waymo ML Engineer interview that leaned heavily into GPU/systems territory. The questions were around kernel optimization, memory layout, and fusion techniques, which felt more like a systems programming screen than a typical ML role.

Questions Asked (3)

Q1

How would you approach optimizing a compute kernel for performance on modern hardware?

Technical Trade-offsSystem Design
Author's notes

Talked through memory access patterns, occupancy, and reducing warp divergence.

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AI HintsAI Generated

Suggested Approach

Start by clarifying the kernel's purpose, performance goals, and hardware target. Then describe a systematic optimization process: profile to identify bottlenecks, apply targeted optimizations (e.g., memory, compute, parallelism), and validate improvements with benchmarks. Emphasize iterative refinement and trade-offs.

Pro tip: Always measure before optimizing—use profiling tools to avoid guessing. Also, consider the roofline model to quickly assess whether you're memory- or compute-bound, which guides where to focus efforts.

1. Understand the Kernel and Goals

Clarify what the kernel does, its current performance, and the target metrics (latency, throughput, power). Identify constraints like hardware (CPU/GPU/TPU), memory hierarchy, and precision requirements.

2. Profile and Analyze Bottlenecks

Use profiling tools (e.g., NVIDIA Nsight, perf, VTune) to measure execution time, memory bandwidth, compute utilization, and stalls. Determine if the kernel is memory-bound, compute-bound, or latency-bound.

3. Apply Targeted Optimizations

Based on the bottleneck, apply optimizations: improve memory access patterns (coalescing, tiling), increase compute efficiency (vectorization, FMA), exploit parallelism (threads, SIMD), and reduce overhead (loop unrolling, fusion).

4. Validate and Iterate

Benchmark the optimized kernel against the baseline, ensuring correctness. Analyze new bottlenecks and repeat the process until performance goals are met or diminishing returns occur.

Key Points to Mention

  • Profiling tools and metrics (e.g., roofline model, occupancy, memory bandwidth)
  • Memory hierarchy optimization (caching, tiling, coalescing)
  • Compute optimization (vectorization, instruction-level parallelism, FMA)
  • Parallelism and concurrency (threads, SIMD, GPU warps)
  • Trade-offs between latency, throughput, and resource usage
  • Hardware-specific features (e.g., tensor cores, DMA, shared memory)

AI-generated suggestions, not part of the candidate's original notes. May be inaccurate — verify before relying on them.

Q2

What memory layout considerations matter when designing data structures for GPU workloads?

Technical Trade-offsSystem Design
Author's notes

AoS vs SoA came up immediately, which felt like the obvious entry point.

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AI HintsAI Generated

Suggested Approach

Start by contrasting CPU and GPU memory hierarchies, emphasizing the massive parallelism and bandwidth constraints of GPUs. Then discuss how data structure design must account for coalesced memory access, alignment, and minimizing divergence. Finally, tie it back to ML workloads at Waymo, such as point cloud processing or neural network inference, where these considerations directly impact performance.

Pro tip: Demonstrate awareness of real-world trade-offs by mentioning that optimal GPU data structures often require restructuring data from AoS to SoA, but this can increase memory footprint and complexity. Also, note that profiling tools like Nsight can validate assumptions.

1. Understand GPU memory hierarchy

Explain the differences between global, shared, and local memory, and how latency and bandwidth vary. Highlight the importance of coalesced access to global memory.

2. Analyze access patterns

Discuss how data layout (AoS vs SoA) affects memory coalescing and cache utilization. Emphasize that SoA is often preferred for GPU workloads.

3. Consider alignment and padding

Explain how misaligned data can cause uncoalesced accesses and wasted bandwidth. Mention the benefits of aligning data to 128-byte boundaries.

4. Minimize divergence and bank conflicts

Describe how shared memory bank conflicts and warp divergence can serialize execution. Suggest techniques like padding shared memory arrays and avoiding conditional branching.

5. Relate to ML workloads

Connect these considerations to specific ML tasks, such as sparse matrix operations, point cloud processing, or tensor operations, and discuss trade-offs in performance and memory usage.

Key Points to Mention

  • Memory coalescing: ensuring adjacent threads access adjacent memory locations to maximize bandwidth.
  • AoS vs SoA: structure of arrays often improves coalescing for GPU workloads.
  • Shared memory bank conflicts: padding can avoid conflicts and improve throughput.
  • Alignment: aligning data to 128-byte boundaries to enable efficient memory transactions.
  • Warp divergence: minimizing divergent branches to avoid serialization.
  • Trade-offs: restructuring data may increase memory usage or complexity, requiring profiling to validate.

AI-generated suggestions, not part of the candidate's original notes. May be inaccurate — verify before relying on them.

Q3

Explain kernel fusion and when you would or wouldn't apply it.

Technical Trade-offsSystem Design
Author's notes

This one tripped me up more than I expected.

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AI HintsAI Generated

Suggested Approach

Start by defining kernel fusion as combining multiple operations into a single GPU kernel to reduce memory traffic and launch overhead. Then discuss when it's beneficial (e.g., element-wise chains, memory-bound ops) and when it's not (e.g., complex control flow, divergent branches). Finally, tie it to real-world ML workloads like those at Waymo, emphasizing trade-offs in performance, compilation complexity, and hardware utilization.

Pro tip: Mention that fusion decisions should be guided by profiling: measure memory bandwidth and kernel launch overhead to identify fusion opportunities, and beware of over-fusion leading to register pressure or reduced occupancy.

1. Define kernel fusion

Explain that kernel fusion is a compiler optimization that merges multiple operations into a single kernel, reducing global memory reads/writes and kernel launch overhead.

2. Explain benefits

Highlight performance gains: reduced memory bandwidth usage, lower latency from fewer kernel launches, and better instruction-level parallelism.

3. Identify when to apply

Discuss scenarios like chains of element-wise operations (e.g., activation functions), memory-bound workloads, and small operations where launch overhead dominates.

4. Identify when not to apply

Mention cases with complex control flow, divergent branches, large intermediate tensors that don't fit in registers/shared memory, or when fusion increases register pressure and reduces occupancy.

5. Relate to ML systems

Connect to ML engineering: fusion is common in frameworks like TensorFlow XLA, PyTorch JIT, and TVM; in autonomous driving, fusion can optimize perception and prediction models for latency-critical inference.

Key Points to Mention

  • Memory bandwidth reduction: fusion minimizes global memory traffic by keeping intermediate results in registers or shared memory.
  • Kernel launch overhead: fewer kernels mean less CPU-GPU synchronization and launch latency.
  • Applicability: best for element-wise operations, reductions, and memory-bound workloads; less effective for compute-bound or divergent operations.
  • Trade-offs: increased register pressure, potential occupancy reduction, and compilation complexity.
  • Tools and frameworks: XLA, TVM, TensorRT, and PyTorch's nvFuser automatically apply fusion; understanding their heuristics is key.
  • Profiling-driven decision: use tools like Nsight Systems or nvprof to identify fusion opportunities and validate gains.

AI-generated suggestions, not part of the candidate's original notes. May be inaccurate — verify before relying on them.