This one stretched longer than I thought it would.
Start by defining the read-after-write (RAW) hazard in a classic 5-stage pipeline, then explain the main solutions: forwarding (bypassing), stalling (pipeline interlock), and register file write-then-read in the same cycle. Compare their trade-offs in terms of performance, hardware complexity, and impact on clock frequency, and conclude with how ARM processors typically balance these.
Pro tip: Mention that forwarding alone cannot resolve the load-use hazard, which requires one stall cycle; this shows you understand the limits of forwarding and the need for a combined approach.
Explain that a RAW hazard occurs when an instruction reads a register that a previous instruction has not yet written back, causing incorrect data to be read.
Describe forwarding (bypassing) from EX/MEM or MEM/WB to EX, stalling the pipeline until the data is available, and writing the register file in the first half of the cycle and reading in the second half.
Compare forwarding (low performance impact but added muxes and longer critical path), stalling (simple but reduces IPC), and register file timing (requires fast write/read but no extra stalls).
Highlight that a load followed by a dependent instruction cannot be fully resolved by forwarding alone; one stall cycle is typically needed, and some architectures use a delayed load slot.
Summarize that most modern pipelines, including ARM's, use forwarding plus a single stall for load-use hazards, balancing performance and hardware cost.
AI-generated suggestions, not part of the candidate's original notes. May be inaccurate — verify before relying on them.