I knew level shifters were needed and said so immediately, but I fumbled on the isolation cell placement.
Start by clarifying that this is a clock domain and power domain crossing, so you need synchronization, isolation, and level shifting. Then walk through the signal path from source to destination, specifying the required cells at each stage and their power domains, and finally discuss reset strategies for both domains.
Pro tip: Emphasize that the synchronizer must be in the destination domain and that isolation cells must be placed on the source side of the level shifter to prevent floating signals when the source is powered down. Also, mention that reset synchronization is crucial to avoid metastability and that the reset for the destination flops should be synchronized to the destination clock.
Determine that the signal crosses from power domain A to B, which may have different voltages and can be independently power-gated. This requires isolation, level shifting, and synchronization.
In domain A, the registered signal is launched. Add an isolation cell (clamp) on the output to hold a known value when A is powered down. If voltage differs, add a level shifter from A to B after isolation.
In domain B, the signal must be synchronized to B's clock using a two-flop synchronizer (or more for high MTBF). The synchronizer flops must be on the always-on rail if B can be powered down, or on B's switchable rail if B is always on when receiving.
Source reset: ensure the source flop resets to a known state. Destination reset: synchronize the reset de-assertion to B's clock and ensure the synchronizer flops are reset to a known state. Use asynchronous assert, synchronous de-assert reset synchronizers.
Isolation cells and level shifters that interface with A must be powered by A's rail (or always-on if A can be off). Synchronizer flops must be powered by B's rail (or always-on if B can be off). Ensure no floating signals when either domain is off.
AI-generated suggestions, not part of the candidate's original notes. May be inaccurate — verify before relying on them.
First, clarify the ordering and data-width requirements: if the control signal is a single-bit event with ordering, a request/ack handshake is the safest choice; if it's multi-bit data with ordering, use an async FIFO. Then justify why two-flop or pulse-to-toggle are insufficient due to ordering violations, and specify the STA/CDC constraints (set_false_path, set_max_delay -datapath_only, ASYNC_REG) to ensure correct synchronization.
Pro tip: Emphasize that ordering is preserved by the handshake protocol itself, not by timing constraints; constraints only ensure metastability is contained. Also mention that for multi-bit control, you must use a FIFO or handshake with a stable data bus, never a two-flop synchronizer per bit.
Determine if the control signal is single-bit or multi-bit, and whether it's a pulse or level. This dictates the viable CDC schemes.
If ordering between multiple control signals or data is required, two-flop and pulse-to-toggle cannot guarantee it; handshake or async FIFO are needed.
For single-bit ordered control, choose request/ack handshake; for multi-bit ordered data, choose async FIFO. Justify why others fail.
Apply set_false_path or set_max_delay -datapath_only on synchronizer paths, set ASYNC_REG on synchronizer flops, and constrain handshake/FIFO control paths appropriately.
Run CDC checks, ensure no reconvergence, and document the chosen scheme and constraints for review.
AI-generated suggestions, not part of the candidate's original notes. May be inaccurate — verify before relying on them.
Honestly a bit of a relief after the async question.
First clarify that sharing a clock eliminates clock-domain crossing (CDC) issues, so you can drop synchronization constraints and focus on intra-clock timing. Then explain how you would verify timing using static timing analysis (STA) with a single clock constraint, while still considering skew, jitter, and other intra-clock effects.
Pro tip: Emphasize that even with a shared clock, you must account for clock skew and jitter, and that proper timing constraints (like create_clock and set_clock_uncertainty) are still essential for accurate STA.
Confirm that A and B are synchronous to the same clock and identify any remaining timing concerns such as skew, jitter, and combinational path delays.
Drop CDC-related constraints (e.g., set_max_delay -datapath_only, set_false_path between domains) and keep setup/hold, clock uncertainty, and input/output delays relative to the shared clock.
Use static timing analysis (STA) with a single clock definition, ensuring all paths are analyzed for setup and hold with appropriate derating and uncertainty.
Account for clock skew and jitter by adding uncertainty margins, and verify that the clock tree synthesis (CTS) balances the clock to both endpoints.
Run gate-level simulation with timing annotations and, if possible, validate on hardware using on-chip timing monitors or oscilloscopes to confirm margins.
AI-generated suggestions, not part of the candidate's original notes. May be inaccurate — verify before relying on them.
Structure your answer by first addressing the dual CDC crossings (A→B and B→A) with proper synchronization and timing closure, then discuss power domain isolation and retention strategies, and finally cover verification with UPF/CPF and simulation. Emphasize the trade-offs and the need for a holistic approach that considers both functional and power intent.
Pro tip: Mention that the isolation cell's power domain and control signal must be carefully chosen to avoid glitches during power-up/down, and that verification should include both static checks (UPF lint) and dynamic simulation with power-aware testbenches.
Identify the two CDC paths: A→B and B→A. For each, determine the clock relationships (synchronous, asynchronous, or mesochronous) and apply appropriate synchronization (e.g., 2-flop synchronizer, handshake, or FIFO). Ensure timing closure by constraining both paths in STA, including false paths or multicycle paths as needed.
When domain B is powered off, the returning signal must be isolated to prevent floating or contention. Choose clamp value (0, 1, or last value) based on system requirements: 0/1 for safe default, last value for retention. High-Z is rarely used for internal signals due to noise sensitivity. Consider using isolation cells with clamp values and retention flops if needed.
Isolation logic should be placed in the always-on domain (domain A) or in a separate always-on power domain, so it remains powered when B is off. The isolation control signal must also be in an always-on domain. Ensure the isolation cell's power supply is from the always-on domain to avoid glitches.
Define a power sequence: before powering down B, assert isolation enable to clamp the B→A signal. After powering up B, wait for B's clocks and resets to stabilize, then de-assert isolation. For retention, save state before power down and restore after power up. Ensure the sequence is controlled by an always-on power management unit.
Use UPF/CPF to specify power domains, isolation, retention, and power states. Run static checks (UPF lint, domain crossing checks) and dynamic simulation with power-aware testbenches that exercise power transitions. Verify that isolation and retention behave correctly and that no glitches or contention occur.
AI-generated suggestions, not part of the candidate's original notes. May be inaccurate — verify before relying on them.