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NVIDIA·Software Engineer·Onsite - System Design / Architecture·Senior

Senior
Jul 2026

Summary

NVIDIA system design round for a software engineer role, heavily focused on compiler internals. The question was brutally specific and I spent most of the time trying to remember what SSA even stood for before getting into the actual design.

Questions Asked (1)

Q1

Design a shader compiler that takes GLSL or HLSL as input and outputs SPIR-V or native ISA. Walk through the full pipeline: lexing, parsing to AST, conversion to SSA-based IR, optimization passes like constant folding, CSE, and dead-code elimination, then register allocation and final code generation. Also describe how you'd test such a system using differential and property-based testing.

System DesignTechnical Trade-offsAlgorithms & Data Structures
Author's notes

This was one question but it's basically five questions stapled together.

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AI HintsAI Generated

Suggested Approach

Structure your answer as a top-down walkthrough of the compiler pipeline, from front-end parsing to back-end code generation, emphasizing the key transformations and optimizations at each stage. Highlight the trade-offs involved in design decisions, such as IR choice and optimization aggressiveness, and explain how you would validate correctness with differential and property-based testing. Conclude by tying your approach to NVIDIA's context, focusing on performance and reliability.

Pro tip: Demonstrate awareness of real-world constraints: mention that shader compilers must balance aggressive optimization with compile-time latency, and that differential testing against a reference compiler (like glslang or DXC) is crucial for catching subtle bugs.

1. Front-end: Lexing and Parsing

Describe how to tokenize the input GLSL/HLSL source and parse it into an abstract syntax tree (AST), handling language-specific features like preprocessor directives and type qualifiers. Mention the use of parser generators (e.g., ANTLR) or hand-written recursive descent parsers for performance and error recovery.

2. Middle-end: IR Construction and Optimization

Explain converting the AST into a typed, SSA-based intermediate representation (IR) to enable effective optimizations. Detail key passes: constant folding, common subexpression elimination (CSE), dead code elimination (DCE), and possibly loop optimizations, noting the order and interaction between passes.

3. Back-end: Register Allocation and Code Generation

Cover lowering the optimized IR to machine code, including instruction selection, register allocation (e.g., graph coloring or linear scan), and scheduling. Discuss target-specific considerations for SPIR-V versus native ISA, such as handling vector types and hardware constraints.

4. Testing Strategy: Differential and Property-Based

Outline a testing approach that combines differential testing (comparing outputs against a reference compiler or interpreter) and property-based testing (generating random shaders and checking invariants like semantic equivalence). Emphasize fuzzing and automated test case reduction for debugging.

5. Trade-offs and Practical Considerations

Summarize key trade-offs: optimization level vs. compile time, IR complexity vs. ease of analysis, and portability vs. performance. Relate these to NVIDIA's needs, such as supporting multiple shader languages and targets while ensuring correctness and performance.

Key Points to Mention

  • SSA form and its benefits for optimization (e.g., simplified def-use chains)
  • Specific optimization passes: constant folding, CSE, DCE, and their ordering
  • Register allocation algorithms: graph coloring vs. linear scan, and handling spilling
  • SPIR-V as an intermediate target and its role in Vulkan/OpenGL
  • Differential testing against reference compilers (e.g., glslang, DXC) and property-based testing with random shader generation
  • Handling of shader-specific features: uniforms, attributes, control flow, and precision qualifiers

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