NVIDIA·Data Scientist·Technical Phone Screen
May 2026
Technical screen for a Data Scientist role at NVIDIA, heavily GPU-focused. The whole thing was basically a deep dive into CUDA internals and GEMM kernel optimization, which felt more like a GPU systems engineer interview than anything data science adjacent.
- Walk through CUDA's execution model: grids, blocks, warps, and threads. How do they relate to each other and to the hardware?
- Describe CUDA's memory hierarchy: global, shared, registers, constant, and texture memory. What are the performance implications of each?
- What is occupancy in CUDA and how do you reason about it when designing a kernel?
- Design a naive single-precision GEMM kernel for C = A x B, then walk through how you would optimize it step by step.
- How do you choose grid and block dimensions for a GEMM kernel, and how do you handle matrix sizes that aren't multiples of your tile size?
- How would you compare your custom GEMM kernel's throughput against cuBLAS?
- How would you overlap host-to-device memory transfers with GPU compute using CUDA streams and pinned memory?
- How do you measure achieved occupancy, arithmetic intensity, and memory bandwidth for a CUDA kernel?
“I had this down pretty well.” The rest of the author's notes on Data Scientist interview at NVIDIA, Technical Phone Screen round, covers how they worked through the question, what the panel pushed back on, and what they would do differently.
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